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INTEGRATED CIRCUITS
DATA SHEET
SAA4995WP PANorama-IC (PAN-IC)
Preliminary specification File under Integrated Circuits, IC02 1997 Jun 10
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
FEATURES * Horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0.5 and 2 (in 384 steps) * Dynamic sample rate conversion for panorama mode display e.g. 4 : 3 material on a 16 : 9 display * Dynamic sample rate conversion for amaronap mode display of e.g. 16 : 9 material on a 4 : 3 display * Operates with 1fh and 2fh * Programmable via microcontroller SNERT (Synchronous No parity Eight bit Receive Transmit) bus. GENERAL DESCRIPTION
SAA4995WP
The PAN-IC is an add-on IC to be used, for example, between analog-to-digital conversion and a serial (field) memory. The device performs the following tasks: * Linear horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0.5 and 2 * Dynamic sample rate conversion for panorama mode display of e.g. 4 : 3 material on a 16 : 9 display * Dynamic sample rate conversion for amaronap mode display of e.g. 16 : 9 material on a 4 : 3 display. The PAN-IC has the ability to increase the data rate from the ADC to a maximum of twice the data rate at the output. To achieve this a clock rate at twice the normal output clock rate is needed to write data to the memory. All actions to generate a lower data rate, produces disable cycles in Write Enable (WE).
QUICK REFERENCE DATA SYMBOL VDD IDD fCLK Tamb supply voltage supply current operating clock frequency operating ambient temperature PARAMETER - - 0 MIN. 4.5 5 110 - - TYP. - 33 70 MAX. 5.5 V mA MHz C UNIT
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA4995WP PLCC44 DESCRIPTION plastic leaded chip carrier; 44 leads VERSION SOT187-2
1997 Jun 10
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
BLOCK DIAGRAM
SAA4995WP
handbook, full pagewidth
CL16 5
CLK 31
VDD1 10
GND1 12
VDD2 15
GND2 16
VDD3 33
GND3 30
VDD4 6
GND4 32
YI7 to YI0
37 to 44
SECAM NOTCH
MUX
VPD FRONT-END
VPD BACK-END
29 to 22
YO7 to YO0
CL16 UI1/UI0 and VI1/VI0 1 to 4
notch
CLK VPD FRONT-END VPD BACK-END 21 to 18 VO0/VO1 and UO0/UO1
SAA4995WP
CL16 '0' C1 C2 C0 17 WEI 7 LINE CONTROL 14 WEO WEod CLK UV MUX INTEGRATOR INTEGRATOR Y DTO
+
out-phase
in-phase
CL16
CLK X0r X1r X2r X0I X1I X2I
13 notch SPL init 11 C0 C1 C2 8 TEST 9 SCANIN
T1 T0
SNDA SNCL VRST
34 35 36 SNERT BUS INTERFACE
MGK176
Fig.1 Block diagram.
1997 Jun 10
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
PINNING SYMBOL UI1 UI0 VI1 VI0 CL16 VDD4 WEI TEST SCANIN VDD1 T0 GND1 T1 WEod VDD2 GND2 WEO VO0 VO1 UO0 UO1 YO0 YO1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DESCRIPTION U input bit 1 U input bit 0 V input bit 1 V input bit 0 half system clock supply voltage 4 write enable input test mode switch input for scan chain supply voltage 1 test mode switch 0 ground 1 test mode switch 1 write enable odd samples supply voltage 2 ground 2 write enable output V output bit 0 V output bit 1 U output bit 0 U output bit 1 luminance output bit 0 luminance output bit 1 SNCL VRST YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 35 36 37 38 39 40 41 42 43 44 SYMBOL YO2 YO3 YO4 YO5 YO6 YO7 GND3 CLK GND4 VDD3 SNDA PIN 24 25 26 27 28 29 30 31 32 33 34
SAA4995WP
DESCRIPTION luminance output bit 2 luminance output bit 3 luminance output bit 4 luminance output bit 5 luminance output bit 6 luminance output bit 7 ground 3 system clock ground 4 supply voltage 3 data input from interface SNERT bus clock input from interface SNERT bus reset input in the vertical blanking interval luminance input bit 7 luminance input bit 6 luminance input bit 5 luminance input bit 4 luminance input bit 3 luminance input bit 2 luminance input bit 1 luminance input bit 0
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
6 VDD4
2 UI0
1 UI1
handbook, full pagewidth
5 CL16
4 VI0
3 VI1
44 YI0
43 YI1
42 YI2
41 YI3
WEI 7 TEST 8 SCANIN 9 VDD1 10 T0 11 GND1 12 T1 13 WEod 14 VDD2 15 GND2 16 WEO 17
40 YI4
39 YI5 38 YI6 37 YI7 36 VRST 35 SNCL
SAA4995WP
34 SDNA 33 VDD3 32 GND4 31 CLK 30 GND3 29 YO7
UO1 21
YO5 27
YO0 22
YO1 23
YO2 24
YO3 25
YO4 26
UO0 20
YO6 28
VO0 18
VO1 19
MGK175
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION The PAN-IC is an add-on IC to be used, for example, between analog-to-digital conversion and a serial (field) memory. The device performs the following tasks: * Linear horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0.5 and 2 * Dynamic sample rate conversion for panorama mode display of e.g. 4 : 3 material on a 16 : 9 display * Dynamic sample rate conversion for amaronap mode display of e.g. 16 : 9 material on a 4 : 3 display. The PAN-IC has the ability to increase the data rate from the ADC (maximum 16 MHz in a 16/32 MHz concept) to a maximum of twice the data rate. For this, a 32 MHz clock rate is needed to write to the memory. All actions to generate a lower data rate produces disable cycles in write enable. In panorama and amaronap modes, the sample rate conversion factor is modulated along the video line. 1997 Jun 10 5
In the centre of the line a high quality compression (e.g. with a factor 43) has to be made. Towards the sides of the line, more and more expansion and compression respectively is made. The sample rate conversion factor over a line will have a bathtub shape, with parameters illustrated in Fig.3: * X0l and X0r, where in-between a constant data rate is maintained (area I) and starting points from where a curve can be programmed for its 2nd derivative (in areas II and V) * X1l and X1r, points from where a new curve can be programmed for its 2nd derivative (for areas III and IV) * X2l corresponds to the first sample in the output data stream, defined by start of WEI * X2r corresponds to the last sample in the output data stream, defined by the programmed number of samples * C1, which controls the second derivatives of the data rate in areas II and V * C2, which controls the second derivatives of the data rate in areas III and IV.
Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
Interpolation function The interpolation for phase positions between the original samples, is achieved with a variable phase delay filter with 10 taps for luminance signals and 4 taps for chrominance signals. For luminance the PAN-IC supplies samples up to 32 MHz. For chrominance the PAN-IC supplies each U and V samples with a data rate of 8 MHz (max). Processing control in the PAN-IC The compress factor (see Fig.4) at any position in the lines is a function of the dynamically changing DTO-increment. When DTOincr = 255, the sample rate is divided by 2; when DTOincr = 0, the sample rate in the PAN-IC remains unchanged; when DTOincr = -128, the sample rate is doubled. Control of number of samples per line Three possibilities exist for the relationship between the end of WEI and the required number of samples per line for storage in the field memory: * WEI negative edge coincides with the required last sample in the line; standard operation. * WEI negative edge is reached before the present last sample in the line was required; extra dummy WE cycles will be generated at the maximum rate (zoom factor 2) to arrive at the required number of samples per line. * The required number of samples per line is reached before WEI negative edge; the DTO calculations will continue until the required number of samples is reached, but without generation of WE cycles. The programmed number of samples per line is thus always realized, independent of all other controls (unless the line period becomes insufficient to store up to the last sample in a line). When using odd/even sample distribution, the programmed number of samples refers to the number of samples in each data stream. Consequently, the total number of samples is twice as many.
SAA4995WP
There is an offset in the programmed number of samples compared to the effective number of samples per line. * Effective number of Y samples = 4 x (programmed number of samples + 1) * Effective number of UV samples = 1 x (programmed number of samples + 1) SECAM Y notch A notch filter at the Y input of the PAN-IC can be switched on. The purpose of this filter is to prevent artefacts from scan velocity modulation with SECAM inputs. The notch filter is an FIR filter with coefficients (-1 0 3 0 3 0 -1). When fs = 16 MHz, the notch frequency is 4 MHz; the maximum gain of the filter is +3 dB at 2 and 6 MHz. Timing The inputs are related to CL16 (half system clock). This clock is used for reference in the PAN-IC from the CL16 pin. The system clock must have a fixed phase relationship to the CL16 enable signal (one clock system). Relationship of WE to video data WE inputs and outputs may be used with either coincident or advanced WE to video timing (see Fig.5). The advanced WE to video timing is applicable to field memories, such as the SAA4955TJ. The input and output WEs of the PAN-IC can be programmed separately to either timing by the in-phase and out-phase bits. Odd/even sample distribution The PAN-IC usually delivers a complete YUV data stream to one receiving device, e.g. a field memory. Optionally, a data stream can be split into odd and even samples, to be received by two receiving devices. The relationship between Y and UV samples is then non-trivial (see Tables 1 to 4).
1997 Jun 10
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
NO SPLITTING INTO ODD AND EVEN SAMPLE STREAM Table 1 E Y0 UV760 Normal output YUV data stream O Y1 UV540 E Y2 UV320 O Y3 UV100 E Y4 UV764 O Y5 UV544 E Y6 UV324 O Y7 UV104 E Y8 UV768 O Y9 UV548
SAA4995WP
E Y10 UV328
O Y11 UV108
E Y12 UV7612
SPLITTING INTO ODD AND EVEN SAMPLE STREAM Keeps corresponding parts of the UV samples in one stream (UV0, UV8, etc. in even stream and UV4, UV12, etc. in odd stream): The odd data stream misses two samples at the start of a line and has two dummy samples at the end of the line, to keep the UV format correct and maintain the same line length as for the even stream (In the odd stream, the last two Y samples and the last U and V samples of a line are not valid). Table 2 E Y0 UV760 Table 3 - - - Even YUV data stream - - - E Y2 UV540 - - - E Y4 UV320 - - - E Y6 UV100 - - - E Y8 UV768 - - - E Y10 UV548 - - - E Y12 UV3212
Odd YUV data stream - - - - - - - - - - - - O Y5 UV764 - - - O Y7 UV544 - - - O Y9 UV324 - - - O Y11 UV10
4
- - -
The even and odd data streams given in Tables 2 and 3 can be distributed to two receiving devices with input enable facilities. A separate input signal for each of the receiving devices must then be applied while the even YUV data stream and odd YUV data stream are again combined. COMBINED ODD/EVEN OUTPUT YUV DATA STREAM Table 4 E Y0 UV76
0
Distribution with odd/even input enable signals - - - E Y2 UV54
0
- - -
E Y4 UV32
0
- Y5 UV764
E Y6 UV100
O Y7 UV544
E Y8 UV758
O Y9 UV324
E Y10 UV548
O Y11 UV10
4
E Y12 UV328
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
handbook, full pagewidth
active period IV V I II III
area:
sample rate
C2 C1 C0 C1
C2
positions:
X2I
X1I
X0I
X0r
X1r
X2r
MGK177
Fig.3 Panorama mode.
handbook, full pagewidth
MGK178
2 compress factor
1
0.5
-256
-128
0
DTOincr
256
Fig.4 Compress factor.
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
handbook, full pagewidth CL16
WEI
with in-phase = 0
WEI YUVI
with in-phase = 1
CLK WEO/WEod
with out-phase = 0
WEO/WEod YUVO
with out-phase = 1
MGK179
Fig.5 WE timing.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD Vi, Vo Io/out P/out Tstg Tamb VESD PARAMETER supply voltage input and output voltages output current per output pin power dissipation per output pin storage temperature operating ambient temperature electrostatic handling for all pins note 1 note 2 Notes 1. Human body model: C = 100 pF, R = 1.5 k, V = 2 kV. 2. Machine model: C = 200 pF, R = 0 , V = 300 V. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 50 UNIT K/W CONDITIONS MIN. -0.5 -0.5 - - -55 -40 - - MAX. +6.5 VDD + 0.5 20 100 +140 +85 2000 300 V V mA mW C C V V UNIT
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
CHARACTERISTICS VDD = 5.0 V; Tamb = 25 C; unless otherwise specified. SYMBOL VDD IDD fCLK fCL16 VIL VIH Ci VOL VOH tsu(i)(D) th(i)(CL16) tsu(i)(CL16) th(i)(CL16) th(o) td Tamb Tj PARAMETER supply voltage supply current operating frequency (CLK) operating frequency (CL16) LOW level input voltage HIGH level input voltage input capacitance LOW level output voltage HIGH level output voltage input set-up time with respect to CL16 rising edge input hold time with respect to CL16 rising edge input set-up time with respect to CLK rising edge input hold time with respect to CLK rising edge output hold time with respect to CLK output delay time with respect to CLK operating ambient temperature junction temperature Io = 4 mA Io = -4 mA except pins SNDA, SNCL, VRST and CLK; see Fig.6 except pins SNDA, SNCL, VRST and CLK; see Fig.6 see Fig.6 see Fig.6 CL = 7 pF CL = 15 pF CONDITIONS MIN. 4.5 - - - - 2.0 - - 2.6 8 0 7 3 5 - 0 -
SAA4995WP
TYP. 5 110 -
1 2fCLK
MAX. 5.5 - 33 - 0.8 VDD 15 0.4 - - - - - - 19 70 125
UNIT V mA MHz MHz V V pF V V ns ns ns ns ns ns C C
- - 10 - 3.4 - - - - - - - -
handbook, full pagewidth CLK
th(i)(CL16) tsu(i)(CL16) CL16 tsu(i)(CL16)
th(i)(CL16)
data input tsu(i)(D) th(i)(D) data output data valid th(o) td data valid
MGK180
Fig.6 Clock timing.
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
MICROCONTROLLER BUS TIMING (SNERT BUS) SYMBOL Tcy(SNCL) tsu(i) th(i) th(o)(D) td PARAMETER SNCL cycle time input data set-up time input data hold time output data hold time output data delay time see Fig.7 see Fig.7 see Fig.7 see Fig.7 see Fig.7 CONDITIONS
SAA4995WP
MIN. 1 90 50 0 -
MAX. - - - - 700
UNIT s ns ns ns ns
handbook, full pagewidth
Tcy(SNCL)
SNCL tsu(i) SNDA (receiver mode) SNDA (transmitter mode) LSB td
data valid data valid data valid data valid data valid
MGK181
th(i)
th(o)(D)
Fig.7 SNERT bus interface timing.
MICROCONTROLLER BUS CONTROL (SNERT BUS) The following control table applies (Table 5), for control via the microcontroller bus (SNERT bus, consisting of SNCL, SNDA and VRST signals). Data communication is by writing to the PAN-IC (address 40H to 48H) and reading from it (address 49H) Table 5 SNERT-bus control FUNCTION X1l X0l X0r X1r output samples per line # OF BITS 8 8 8 8 8 BIT POSITION 7:0 7:0 7:0 7:0 7:0 REMARKS definition of X1l with a resolution of 4 samples; see Fig.3 and note 1 definition of X0l with a resolution of 4 samples; see Fig.3 and note 1 definition of X0r with a resolution of 4 samples; see Fig.3 and note 1 definition of X1r with a resolution of 4 samples; see Fig.3 and note 1 resolution of 4 luminance samples; actual # samples = (programmed # samples + 1) x 4; note 2
ADDRESS (HEX) 40 41 42 43 44
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SAA4995WP
ADDRESS (HEX) 45 46
FUNCTION C0 C1 distribution
# OF BITS 8 6 1 6 1 1 1 1 1 1 1 1 1 1 8 read bits
BIT POSITION 7:0 5:0 6 5:0 6 7 0 1 2 3 4 5 6 7 7:0
REMARKS constant DTOincr value for area I, MSB extended by zoom bit at address 48 (twos complement value); see Figs 3 and 4 2nd derivatives for DTOincr for areas II and V (twos complement value); see Figs 3 and 4 enables odd/even sample distribution; see Tables 1 to 4 2nd derivatives for DTOincr for areas III and IV (twos complement value) test bit, must be logic 0 in normal operation SECAM Y notch on/off (logic 1 = on, logic 0 = off) logic 1 = zoom, logic 0 = compress in area I logic 1 = shifted relation WE_IN to input data; see Fig.5 logic 1 = shifted relation WEO/WEod to output data; see Fig.5 circuitry is initialized at VRST pulse new settings are activated at VRST pulse compression curve is kept from last active line in field test bit, must be logic 0 in normal operation adapt bit, must be logic 0 in normal operation PAN-IC identifies by pulling all bits LOW (hardware cluck)
47
C2 test 1 notch
48
zoom bit in-phase out-phase init vrst_xfer keep test 2 adapt
49 Notes
identify read
1. For a symmetrical bathtub curve Xnl + Xnr = output samples per line + 1. 2. WEI falling edge delay to the WEO latest sample should not be equal to the pipeline delay. This can be controlled with the WEI length via the microcontroller. TEST The test mode can be chosen via pins TEST, T0 and T1. Table 6 Test modes PIN NAME MODE TEST Functional test Test mode on Note 1. X = don't care. 0 1 T1 X(1) X(1) T0 X(1) X(1)
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
PACKAGE OUTLINE PLCC44: plastic leaded chip carrier; 44 leads
SAA4995WP
SOT187-2
eD y X A ZE
eE
39
29 28
40
bp b1 wM
44
1
pin 1 index
E
HE A
e
A4 A1 (A 3)
k
6
18 k 1 Lp 7 e D HD 17 ZD B vMB detail X vM A
0
5 scale
10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.05
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.630 0.630 0.695 0.695 0.048 0.057 0.021 0.032 0.656 0.656 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.12 0.590 0.590 0.685 0.685 0.042 0.040 0.013 0.026 0.650 0.650
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT187-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-25
1997 Jun 10
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA4995WP
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
PANorama-IC (PAN-IC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4995WP
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
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15
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/20/01/pp16
Date of release: 1997 Jun 10
Document order number:
9397 750 01609

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